PLENARY SPEAKERS
Associate Professor, Materials Science and Engineering, National University of Singapore
Dr. Mario Lanza is an Associate Professor of Materials Science and Engineering at the National University of Singapore, since August 2024. He got the PhD in Electronic Engineering in 2010 at the Autonomous University of Barcelona, where he won the extraordinary PhD prize. In 2010-2011 he was NSFC postdoctoral fellow at Peking University, and in 2012-2013 he was Marie Curie postdoctoral fellow at Stanford University. On September 2013 he joined Soochow University (in China), where he promoted until the rank of Full Professor. Between October 2020 and July 2024 he was full-time Associate Professor at the King Abdullah University of Science and Technology (in Saudi Arabia), where he became known for his work in the field of nano-electronics. He has published over 200 research articles in top journals like Nature, Science and Nature Electronics, many of them becoming highly cited. He has been plenary, keynote, tutorial and invited speaker in over 150 conferences, and he and his students have received some of the most prestigious awards in the world (like the IEEE Fellow). He has been often consulted by leading semiconductor companies and publishers. He is an active member of the board governors of the IEEE – Electron Devices Society, and has been involved in the technical and management committee of top conferences in the field of electron devices, including IEDM, IRPS and IPFA. He speaks fluently five languages: English, Chinese, German, Spanish and Catalan.
Abstract - Hardware implementations of artificial neural networks (ANNs)—the most advanced of which are made of millions of electronic neurons interconnected by hundreds of millions of electronic synapses—have achieved higher energy efficiency than classical computers in some small-scale data-intensive computing tasks. State-of-the-art neuromorphic computers, such as Intel’s Loihi or IBM’s NorthPole, implement ANNs using bio-inspired neuron- and synapse-mimicking circuits made of complementary metal–oxide–semiconductor (CMOS) transistors, at least 18 per neuron and six per synapse. Simplifying the structure and size of these two building blocks would enable the construction of more sophisticated, larger and more energy-efficient ANNs. In this talk I will explain how a single CMOS transistor can exhibit neural and synaptic behaviours if it is biased in a specific (unconventional) manner. By connecting one additional CMOS transistor in series, we build a versatile 2-transistor-cell that exhibits adjustable neuro-synaptic response (which we named neuro-synaptic random access memory cell, or NS-RAM cell). This electronic performance comes with a yield of 100% and an ultra-low device-to-device variability, owing to the maturity of the silicon CMOS platform used—no materials or devices alien to the CMOS process are required. These results represent a short-term solution for the implementation of efficient ANNs and an opportunity in terms of CMOS circuit design and optimization for artificial intelligence applications.
Dr. Chong Leong, Gan received his B.S. degree in Chemical Engineering from National University of Malaysia in 2000, M.S. degree in Chemical Instrumentation in 2003 from University Science Malaysia, and Ph.D. in Nanoelectronic Engineering from University Malaysia Perlis, Malaysia in 2015. He is Senior Member of IEEE, Fellow of Institution of Engineering and Technology, Fellow of Institute of Materials, Minerals & Mining, UK., Fellow of Institute of Physics, UK., and Royal Society of Chemistry, UK. Since 2000, he has been with Silterra Malaysia, Quality and Reliability MTS with Altera, Product Engineering with Osram Opto-Semiconductors, Broadcom, Senior R&D Engineering Manager with SanDisk and currently working as Package Characterization Director with Micron Taiwan. He is recipient of IEEE EPS Distinguish Technical Leadership Certificate in 2021, Emerald Outstanding Journal Reviewer in 2021 and ASME JEP Reviewer of the Year in 2022. His research interests including semiconductor packaging reliability, electronic packaging materials characterization, nanomaterials, and radiation reliability. He has published more than 75 international journal articles, 1 book with Springer Publisher. CL serves as Editorial boards with more than 25 international journals, Guest Editor with Elsevier Materials Science in Semiconductor Processing and Emerald Microelectronics Internal journals. He has 30 patents issued/ filing in US and China patent offices..
Abstract - With the recent innovation of Open AI (Artificial Intelligence) and ChatGPT deployment, this increase has triggered the growth of data center infrastructure as processing, storage, and communication system in the digital world. The data center itself has contributed 1.5 % to the total world electricity consumption and this is expected to increase with time. Continuous higher demand for low power, larger data storage and faster transport speed are pushing the memory key suppliers to provide the advanced packages solutions such as NAND-Based MCP (Multiple Chip Package), HBM (High Bandwidth Memory), immersion-cooled and future cryogenic memory computing in AI Datacenters. This talk lays out the technical requirements of semiconductor electronics materials roadmaps, development, and properties with closer interactions on packaging robustness. It encompasses its package strength, component and solder joint reliability, package warpage performance, thermal dissipation as well as radiation induced soft errors, which become more important due to higher susceptibility of these packages to external thermal-mechanical stresses in AI datacenter applications. Evolution of these key assembly materials will be discussed in terms of its technical challenges and enabling reasoning as well as possible failure modes and mechanisms to address the needs and callouts for identifying those key materials characteristics which are critical to memory system level packaging.